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PETER WANG

Hardware Architect | ML Engineer

Let's Connect View Resume

UC Berkeley

B.S. Computer Science | Minor in Electrical Engineering

2025 Jim & Donna Gray Endowment Award Recipient

Experience Journey

SoC Architecture Intern

Arm | May 2025 - Aug 2025

  • Frontend, ASIC, RTL analysis
  • Cutting-edge chip architecture development

CS Peer Advisor

UC Berkeley | Aug 2024 - Present

  • First official hire as peer advisor for EECS
  • Mentoring next generation of engineers

AI/ML Intern

Honda Research Institute | Jan 2024 - May 2024

  • L2 Ridge Regression for telematics data
  • K-Means clustering for traffic optimization
  • Identified critical energy inefficiencies

Machine Learning Engineer

IEEE | Aug 2020 - Jun 2022

  • Published research in 2021 ISPACS, IEEE
  • NAS framework with gradient optimization
  • 36% training time reduction with CUDA

Technical Arsenal

Python 75%
Java 65%
C/C++ 60%
SQL 65%
Shell/Bash/Vim 55%

Innovation Showcase

🔧

CPU Design & Implementation

Architected a complete RISC-V CPU in Logisim with custom ALU, register files, and comprehensive instruction set validation.

⚡

MOSFET Amplifier Design

Engineered high-performance common-source amplifier with optimized frequency response characteristics using LTSpice simulations.

🧠

AWS Trainium Accelerator

Developed cutting-edge FFNN and Conv2D kernels on AWS Trainium using NKI, pushing boundaries of ML hardware acceleration.

🎯

Branch Predictor Design

Revolutionary perceptron predictor achieving 13% misprediction reduction through advanced weighted history analysis.

💾

Cache System Analysis

Optimized prefetching strategies with adaptive algorithms, maximizing spatial and temporal locality performance.

Let's Build Something Amazing

Ready to push the boundaries of technology together?

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🚀 ACHIEVEMENT UNLOCKED! 🚀